library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Switch is
	port(
		reset_key: in std_logic;
		reset_out: out std_logic;
--        rx_clk: in std_logic;
	 packet_1 : out std_logic_vector(3 downto 0); --test
	 tx_err, tx_val: out std_logic; --test
		clk50   : in std_logic;
        --switch fabric interface
		test_rxd0_fifo_rdreq : out std_logic;
		test_rxd0_fifo_empty : out std_logic;
		test_rxd0_fifo_q : out std_logic_vector(7 downto 0);
		test_rxd0_length_fifo_rdreq : out std_logic;
		test_rxd0_length_fifo_empty : out std_logic;
		test_rxd0_length_fifo_q : out std_logic_vector(11 downto 0);
		
--		rxd1_fifo_rdreq : in std_logic := '0' ;
--		rxd1_fifo_empty : out std_logic;
--		rxd1_fifo_q : out std_logic_vector(7 downto 0);
--		rxd1_length_fifo_rdreq : in std_logic := '0' ;
--		rxd1_length_fifo_empty : out std_logic;
--		rxd1_length_fifo_q : out std_logic_vector(11 downto 0);
--		
--		rxd2_fifo_rdreq : in std_logic := '0' ;
--		rxd2_fifo_empty : out std_logic;
--		rxd2_fifo_q : out std_logic_vector(7 downto 0);
--		rxd2_length_fifo_rdreq : in std_logic := '0' ;
--		rxd2_length_fifo_empty : out std_logic;
--		rxd2_length_fifo_q : out std_logic_vector(11 downto 0);
--		
--		rxd3_fifo_rdreq : in std_logic := '0' ;
--		rxd3_fifo_empty : out std_logic;
--		rxd3_fifo_q : out std_logic_vector(7 downto 0);
--		rxd3_length_fifo_rdreq : in std_logic := '0' ;
--		rxd3_length_fifo_empty : out std_logic;
--		rxd3_length_fifo_q : out std_logic_vector(11 downto 0);
--		--test outputs for observation
		test_rxd0_state_out : out std_logic_vector(1 downto 0);
--		rxd1_state_out : out std_logic_vector(1 downto 0);
--		rxd2_state_out : out std_logic_vector(1 downto 0);
--		rxd3_state_out : out std_logic_vector(1 downto 0);
		
		--inputs from table to SF_table_interface
		test_TSF_DS_PortNum : out STD_LOGIC_VECTOR (1 downto 0); -- in
		test_TSF_OutputP_ready,	test_TSF_Bcast: out STD_LOGIC; -- in
		--outputs to table from SF_table_interface
		test_SFT_req_out: Out STD_LOGIC;
		test_SFT_RDone: Out STD_LOGIC;
		test_SFT_SportN: Out STD_LOGIC_VECTOR(1 downto 0);
		test_SFT_DMac_add_out, test_SFT_SMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);
		--inputs from xmt to SF_fifo2xmt_interface
--		xmt0_wused,	xmt1_wused,	xmt2_wused,	xmt3_wused: in std_logic_vector(12 downto 0);
--		--outputs to xmt from SF_fifo2xmt_interface
--		xmt_all_data: out std_logic_vector (7 downto 0);     -- out to xmt D FIFOs
--		xmt_all_length: out std_logic_vector (11 downto 0);    -- out to xmt L FIFOs
--		xmt_dwreq, xmt_lwreq: out std_logic_vector (3 downto 0); --read/write request to xmt data and length FIFOs

		-- Physical Board ports
		
		rx_clk_p0, 	rx_clk_p1,	rx_clk_p2, 	rx_clk_p3	: IN STD_LOGIC ;
		rxd_p0, 	rxd_p1, 	rxd_p2, 	rxd_p3		: IN STD_LOGIC_VECTOR (3 DOWNTO 0):= "0000";
		rx_dv_p0, 	rx_dv_p1, 	rx_dv_p2, 	rx_dv_p3 	: IN STD_LOGIC := '0';
		rx_er_p0,	rx_er_p1, 	rx_er_p2, 	rx_er_p3  	: IN STD_LOGIC := '0';
		
		TX_EN_P1, TX_ER_P1 	: OUT STD_LOGIC ;
		q_sig_P1			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		TX_clk_sig_P1 		: IN STD_LOGIC ;
        TX_EN_P2, TX_ER_P2 	: OUT STD_LOGIC ;
		q_sig_P2			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		TX_clk_sig_P2 		: IN STD_LOGIC ;
        TX_EN_P3, TX_ER_P3 	: OUT STD_LOGIC ;
		q_sig_P3			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		TX_clk_sig_P3 		: IN STD_LOGIC ;
		TX_EN_P4, TX_ER_P4 	: OUT STD_LOGIC ;
		q_sig_P4			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		TX_clk_sig_P4 		: IN STD_LOGIC 
		
        );  
	end entity;
	
architecture TX_RCV of Switch is
	
	component FPGAtest is
	port(
		clk		: in std_logic;
		output	: out std_logic_vector(3 downto 0);
		transmit_error : out std_logic;
		transmit_valid : out std_logic
	);
	end component;

	component rx_top is
	port(
		clk  	: in	std_logic;
		reset 	: in std_logic;
		-- mii signals
		rx_clk 	: in	std_logic; -- 25 MHz
		rxd 	: in std_logic_vector(3 downto 0);
		rx_dv 	: in std_logic;
		rx_er 	: in std_logic;
		--switch fabric interface
		rxd_fifo_rdreq  : in std_logic;
		rxd_fifo_empty : out std_logic;
		rxd_fifo_q : out std_logic_vector(7 downto 0);
		length_fifo_rdreq : in std_logic;
		length_fifo_empty : out std_logic;
		length_fifo_q : out std_logic_vector(11 downto 0);
		--test outputs for observation
		state_out : out std_logic_vector(1 downto 0)
	);
	end component;
	
	component SwitchFabric is
	port( 							
		clk, reset	: in std_logic;
		--inputs from rcv to SF_rcv_interface
		rcv0_data, 	rcv1_data, 	rcv2_data, 	rcv3_data: in std_logic_vector(7 downto 0);
		rcv0_length,rcv1_length,rcv2_length,rcv3_length: in std_logic_vector(11 downto 0);
		rcv0_qempty,rcv1_qempty,rcv2_qempty,rcv3_qempty: in std_logic;
		--outputs to rcv from SF_rcv_interface
		rcv0_drdreq, 	rcv1_drdreq, 	rcv2_drdreq, 	rcv3_drdreq: out std_logic;
		rcv0_lrdreq, 	rcv1_lrdreq, 	rcv2_lrdreq, 	rcv3_lrdreq: out std_logic;
		--inputs from table to SF_table_interface
		TSF_DS_PortNum : in STD_LOGIC_VECTOR (1 downto 0);
		TSF_OutputP_ready,	TSF_Bcast: in STD_LOGIC;
		--outputs to table from SF_table_interface
		SFT_req_out	: Out STD_LOGIC;
		SFT_RDone	: Out STD_LOGIC;
		SFT_SportN	: Out STD_LOGIC_VECTOR(1 downto 0);
		SFT_DMac_add_out, SFT_SMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);
		--inputs from xmt to SF_fifo2xmt_interface
		xmt0_wused,	xmt1_wused,	xmt2_wused,	xmt3_wused: in std_logic_vector(12 downto 0);
		--outputs to xmt from SF_fifo2xmt_interface
		xmt_all_data: out std_logic_vector (7 downto 0);     -- out to xmt D FIFOs
		xmt_all_length: out std_logic_vector (11 downto 0);    -- out to xmt L FIFOs
		xmt_dwreq, xmt_lwreq: out std_logic_vector (3 downto 0) --read/write request to xmt data and length FIFOs	
	);  
	end component;

	component switchmanagement is
	port(
		clk,reset	: in std_logic;
		request		: in std_logic;
		receive		: in std_logic;
		D_addr, S_addr: in std_logic_vector(7 downto 0);
		inport_num	: in std_logic_vector(1 downto 0);
		outport_num	: out std_logic_vector(1 downto 0);
		ready		: out std_logic;
		broadcast	: out std_logic
	);
	end component;

	component MULTIPORT is
	PORT
	(
--		Interface to PHY P1
		TX_EN_P1,TX_ER_P1	: OUT STD_LOGIC ;
		q_sig_P1			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig_P1		: IN STD_LOGIC ;
		reset				: IN std_logic;				
-- 		Length FIFO signals to SF P1				
		wrclk				: std_logic;
		wrreq_sig_L_P1		: IN STD_LOGIC;
		data_sig_L_P1		: STD_LOGIC_VECTOR (11 DOWNTO 0);				
--		Data FIFO signals to SF	P1
		data_sig_P1			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq_sig_P1		: IN STD_LOGIC ;		
		wrusedw_sig_P1		: OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
--		Interface to PHY P2
		TX_EN_P2,TX_ER_P2	: OUT STD_LOGIC ;
		q_sig_P2			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig_P2		: IN STD_LOGIC ;
-- 		Length FIFO signals to SF P2				
		wrreq_sig_L_P2		: IN STD_LOGIC;
		data_sig_L_P2		: STD_LOGIC_VECTOR (11 DOWNTO 0);				
--		Data FIFO signals to SF	P2
		data_sig_P2			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq_sig_P2		: IN STD_LOGIC ;		
		wrusedw_sig_P2		: OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
--		Interface to PHY P3
		TX_EN_P3,TX_ER_P3	: OUT STD_LOGIC ;
		q_sig_P3			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig_P3		: IN STD_LOGIC ;
-- 		Length FIFO signals to SF P3				
		wrreq_sig_L_P3		: IN STD_LOGIC;
		data_sig_L_P3		: STD_LOGIC_VECTOR (11 DOWNTO 0);				
--		Data FIFO signals to SF	P3
		data_sig_P3			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq_sig_P3		: IN STD_LOGIC ;		
		wrusedw_sig_P3		: OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
--		Interface to PHY P24
		TX_EN_P4,TX_ER_P4	: OUT STD_LOGIC ;
		q_sig_P4			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdclk_sig_P4		: IN STD_LOGIC ;
-- 		Length FIFO signals to SF P4				
		wrreq_sig_L_P4		: IN STD_LOGIC;
		data_sig_L_P4		: STD_LOGIC_VECTOR (11 DOWNTO 0);				
--		Data FIFO signals to SF	P2
		data_sig_P4			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wrreq_sig_P4		: IN STD_LOGIC ;		
		wrusedw_sig_P4		: OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
	);
	end component;
    signal	reset_next: std_logic;
    signal  reset_RX, reset_SF, reset_SM, reset_TX: std_logic;
    signal  clk50_RX, clk50_SF, clk50_SM, clk50_TX: std_logic;
	signal packet_data: std_logic_vector(3 downto 0);
	signal tx_error, tx_valid: std_logic;
	signal	rxd0_fifo_rdreq : std_logic;
	signal	rxd0_fifo_empty : std_logic;
	signal	rxd0_fifo_q 	: std_logic_vector(7 downto 0);
	signal	rxd0_length_fifo_rdreq : std_logic;
	signal	rxd0_length_fifo_empty : std_logic;
	signal	rxd0_length_fifo_q : std_logic_vector(11 downto 0);
	
	signal	rxd1_fifo_rdreq : std_logic := '0' ;
	signal	rxd1_fifo_empty : std_logic := '1' ;
	signal	rxd1_fifo_q 	: std_logic_vector(7 downto 0);
	signal	rxd1_length_fifo_rdreq : std_logic := '0' ;
	signal	rxd1_length_fifo_empty : std_logic := '1' ;
	signal	rxd1_length_fifo_q : std_logic_vector(11 downto 0);
		
	signal	rxd2_fifo_rdreq : std_logic := '0' ;
	signal	rxd2_fifo_empty : std_logic := '1' ;
	signal	rxd2_fifo_q : std_logic_vector(7 downto 0);
	signal	rxd2_length_fifo_rdreq : std_logic := '0' ;
	signal	rxd2_length_fifo_empty : std_logic := '1' ;
	signal	rxd2_length_fifo_q : std_logic_vector(11 downto 0);
		
	signal	rxd3_fifo_rdreq : std_logic := '0' ;
	signal	rxd3_fifo_empty : std_logic := '1' ;
	signal	rxd3_fifo_q 	: std_logic_vector(7 downto 0);
	signal	rxd3_length_fifo_rdreq : std_logic := '0' ;
	signal	rxd3_length_fifo_empty : std_logic := '1' ;
	signal	rxd3_length_fifo_q : std_logic_vector(11 downto 0);
	--test outputs for observation
	signal	rxd0_state_out : std_logic_vector(1 downto 0);
	signal	rxd1_state_out : std_logic_vector(1 downto 0);
	signal	rxd2_state_out : std_logic_vector(1 downto 0);
	signal	rxd3_state_out : std_logic_vector(1 downto 0);
	
	--inputs from table to SF_table_interface
	signal	TSF_DS_PortNum : STD_LOGIC_VECTOR (1 downto 0);
	signal	TSF_OutputP_ready,	TSF_Bcast: STD_LOGIC;
	--outputs to table from SF_table_interface
	signal	SFT_req_out	: STD_LOGIC;
	signal	SFT_RDone	: STD_LOGIC;
	signal	SFT_SportN	: STD_LOGIC_VECTOR(1 downto 0);
	signal	SFT_DMac_add_out, SFT_SMac_add_out : STD_LOGIC_VECTOR(7 downto 0);
	
	-- for transmit
	signal xmt0_wused,	xmt1_wused,	xmt2_wused,	xmt3_wused: std_logic_vector(12 downto 0);
	--outputs to xmt from SF_fifo2xmt_interface
	signal xmt_all_data		: std_logic_vector (7 downto 0);     -- out to xmt D FIFOs
	signal xmt_all_length	:  std_logic_vector (11 downto 0);    -- out to xmt L FIFOs
	signal xmt_dwreq, xmt_lwreq: std_logic_vector (3 downto 0); --read/write request to xmt data and length FIFOs	

	begin
--------------------- Test Team Tx --------------------------	
	FPGAtest_out : FPGAtest port map (
		clk => rx_clk_p0,
		output => packet_data,
		transmit_error => tx_error,
		transmit_valid => tx_valid
	);
--------------------------------------------------------------
------------------- RX Port Mapping --------------------------	
	rx_port0 : rx_top port map (
		clk 			=> clk50_RX, -- clock should be 50MHz
		reset 			=> reset_RX,
		-- mii signals
		rx_clk			=> rx_clk_p0,
		rxd 			=> packet_data, --rxd_p0,
		rx_dv 			=> tx_valid, --rx_dv_p0,
		rx_er 			=> tx_error, --rx_er_p0,
		--switch fabric interface
		rxd_fifo_rdreq 	=> rxd0_fifo_rdreq,
		rxd_fifo_empty 	=> rxd0_fifo_empty,
		rxd_fifo_q 		=> rxd0_fifo_q,
		length_fifo_rdreq => rxd0_length_fifo_rdreq,
		length_fifo_empty => rxd0_length_fifo_empty,
		length_fifo_q 	=> rxd0_length_fifo_q,
		--test outputs for observation
		state_out 		=> rxd0_state_out
	);
	rx_port1 : rx_top port map (
		clk 			=> clk50_RX, -- clock should be 50MHz
		reset 			=> reset_RX,
		-- mii signals
		rx_clk			=> rx_clk_p1,
		rxd 			=> "0000", --rxd_p1,
		rx_dv 			=> '0', --rx_dv_p1,
		rx_er 			=> '0', --rx_er_p1,
		--switch fabric interface
		rxd_fifo_rdreq 	=> rxd1_fifo_rdreq,
		rxd_fifo_empty 	=> rxd1_fifo_empty,
		rxd_fifo_q 		=> rxd1_fifo_q,
		length_fifo_rdreq => rxd1_length_fifo_rdreq,
		length_fifo_empty => rxd1_length_fifo_empty,
		length_fifo_q 	=> rxd1_length_fifo_q,
		--test outputs for observation
		state_out 		=> rxd1_state_out
	);
	rx_port2 : rx_top port map (
		clk 			=> clk50_RX, -- clock should be 50MHz
		reset 			=> reset_RX,
		-- mii signals
		rx_clk			=> rx_clk_p2,
		rxd 			=> "0000", --rxd_p2,
		rx_dv 			=> '0', --rx_dv_p2,
		rx_er 			=> '0', --rx_er_p3,
		--switch fabric interface
		rxd_fifo_rdreq 	=> rxd2_fifo_rdreq,
		rxd_fifo_empty 	=> rxd2_fifo_empty,
		rxd_fifo_q 		=> rxd2_fifo_q,
		length_fifo_rdreq => rxd2_length_fifo_rdreq,
		length_fifo_empty => rxd2_length_fifo_empty,
		length_fifo_q 	=> rxd2_length_fifo_q,
		--test outputs for observation
		state_out 		=> rxd2_state_out
	);
	rx_port3 : rx_top port map (
		clk 			=> clk50_RX, -- clock should be 50MHz
		reset 			=> reset_RX,
		-- mii signals
		rx_clk			=> rx_clk_p3,
		rxd 			=> "0000", -- rxd_p3,
		rx_dv 			=> '0', -- rx_dv_p3,
		rx_er 			=> '0', -- rx_er_p3,
		--switch fabric interface
		rxd_fifo_rdreq 	=> rxd3_fifo_rdreq,
		rxd_fifo_empty 	=> rxd3_fifo_empty,
		rxd_fifo_q 		=> rxd3_fifo_q,
		length_fifo_rdreq => rxd3_length_fifo_rdreq,
		length_fifo_empty => rxd3_length_fifo_empty,
		length_fifo_q 	=> rxd3_length_fifo_q,
		--test outputs for observation
		state_out 		=> rxd3_state_out
	);
--------------------------------------------------------------
--------------- Switch Fabric Port Mapping -------------------	
	SF : SwitchFabric port map ( 							
		clk			=> clk50_SF,
		reset		=> reset_SF,
		--inputs from rcv to SF_rcv_interface
		rcv0_data 	=> rxd0_fifo_q,
		rcv1_data 	=> rxd1_fifo_q,
		rcv2_data 	=> rxd2_fifo_q,
		rcv3_data 	=> rxd3_fifo_q,
		rcv0_length	=> rxd0_length_fifo_q,
		rcv1_length	=> rxd1_length_fifo_q,
		rcv2_length	=> rxd2_length_fifo_q,
		rcv3_length	=> rxd3_length_fifo_q,
		rcv0_qempty	=> rxd0_length_fifo_empty,
		rcv1_qempty	=> rxd1_length_fifo_empty,
		rcv2_qempty	=> rxd2_length_fifo_empty,
		rcv3_qempty	=> rxd3_length_fifo_empty,
		--outputs to rcv from SF_rcv_interface
		rcv0_drdreq	=> rxd0_fifo_rdreq,
		rcv1_drdreq	=> rxd1_fifo_rdreq,
		rcv2_drdreq	=> rxd2_fifo_rdreq,
		rcv3_drdreq	=> rxd3_fifo_rdreq,
		rcv0_lrdreq	=> rxd0_length_fifo_rdreq,
		rcv1_lrdreq	=> rxd1_length_fifo_rdreq,
		rcv2_lrdreq	=> rxd2_length_fifo_rdreq,
		rcv3_lrdreq	=> rxd3_length_fifo_rdreq,

		--inputs from table to SF_table_interface
		TSF_DS_PortNum => TSF_DS_PortNum,
		TSF_OutputP_ready => TSF_OutputP_ready,
		TSF_Bcast 	=> TSF_Bcast,
		--outputs to table from SF_table_interface
		SFT_req_out => SFT_req_out,
		SFT_RDone 	=> SFT_RDone,
		SFT_SportN 	=> SFT_SportN,
		SFT_DMac_add_out => SFT_DMac_add_out,
		SFT_SMac_add_out => SFT_SMac_add_out,
		--inputs from xmt to SF_fifo2xmt_interface
		xmt0_wused 	=> xmt0_wused,
		xmt1_wused 	=> xmt1_wused,
		xmt2_wused 	=> xmt2_wused,
		xmt3_wused 	=> xmt3_wused,
		--outputs to xmt from SF_fifo2xmt_interface
		xmt_all_data => xmt_all_data,
		xmt_all_length => xmt_all_length, -- out to xmt L FIFOs
		xmt_dwreq 	=> xmt_dwreq,
		xmt_lwreq 	=> xmt_lwreq --read/write request to xmt data and length FIFOs	
	); 
--------------------------------------------------------------
--------------- Switch Management Port Mapping ---------------
	SM : switchmanagement port map ( 							
		clk 		=> clk50_SM,
		reset  		=> reset_SM,
		request		=> SFT_req_out,
		receive 	=> SFT_RDone,
		D_addr		=> SFT_DMac_add_out,
		S_addr		=> SFT_SMac_add_out,
		inport_num	=> SFT_SportN,
		outport_num	=> TSF_DS_PortNum,
		ready		=> TSF_OutputP_ready,
		broadcast	=> TSF_Bcast
	); 
--------------------------------------------------------------
------------------ Transmitter Port Mapping ------------------
	Tx : MULTIPORT port map ( 							
--		Interface to PHY P1
		TX_EN_P1 		=> TX_EN_P1,
		TX_ER_P1 		=> TX_ER_P1,
		q_sig_P1 		=> q_sig_P1,
		rdclk_sig_P1 	=> TX_clk_sig_P1,
		reset 			=> reset_TX,
-- 		Length FIFO signals to SF P1				
		wrclk 			=> clk50_TX,
		wrreq_sig_L_P1 	=> xmt_lwreq(0),
		data_sig_L_P1 	=> xmt_all_length,
--		Data FIFO signals to SF	P1
		data_sig_P1		=> xmt_all_data,
		wrreq_sig_P1 	=> xmt_dwreq(0),
		wrusedw_sig_P1	=> xmt0_wused,
--		Interface to PHY P2
		TX_EN_P2		=> TX_EN_P2,
		TX_ER_P2		=> TX_ER_P2,
		q_sig_P2		=> q_sig_P2,
		rdclk_sig_P2	=> TX_clk_sig_P2,
-- 		Length FIFO signals to SF P2				
		wrreq_sig_L_P2	=> xmt_lwreq(1),
		data_sig_L_P2	=> xmt_all_length,
--		Data FIFO signals to SF	P2
		data_sig_P2		=> xmt_all_data,
		wrreq_sig_P2	=> xmt_dwreq(1),
		wrusedw_sig_P2	=> xmt1_wused,
--		Interface to PHY P3
		TX_EN_P3		=> TX_EN_P3,
		TX_ER_P3		=> TX_ER_P3,
		q_sig_P3		=> q_sig_P3,
		rdclk_sig_P3	=> TX_clk_sig_P3,
-- 		Length FIFO signals to SF P3				
		wrreq_sig_L_P3	=> xmt_lwreq(2),
		data_sig_L_P3	=> xmt_all_length,
--		Data FIFO signals to SF	P3
		data_sig_P3		=> xmt_all_data,
		wrreq_sig_P3	=> xmt_dwreq(2),
		wrusedw_sig_P3	=> xmt2_wused,
--		Interface to PHY P24
		TX_EN_P4		=> TX_EN_P4,
		TX_ER_P4		=> TX_ER_P4,
		q_sig_P4		=> q_sig_P4,
		rdclk_sig_P4	=> TX_clk_sig_P4,
-- 		Length FIFO signals to SF P4				
		wrreq_sig_L_P4	=> xmt_lwreq(3),
		data_sig_L_P4	=> xmt_all_length,
--		Data FIFO signals to SF	P2
		data_sig_P4		=> xmt_all_data,
		wrreq_sig_P4	=> xmt_dwreq(3),
		wrusedw_sig_P4	=> xmt3_wused
	); 	
--------------------------------------------------------------	
	
	packet_1 <= packet_data; -- test
	tx_err 	<= tx_error;
	tx_val 	<= tx_valid;
	 
	test_rxd0_fifo_rdreq 		<= rxd0_fifo_rdreq;
	test_rxd0_fifo_empty 		<= rxd0_fifo_empty;
	test_rxd0_fifo_q 			<= rxd0_fifo_q;
	test_rxd0_length_fifo_rdreq <= rxd0_length_fifo_rdreq;
	test_rxd0_length_fifo_empty <= rxd0_length_fifo_empty;
	test_rxd0_length_fifo_q 	<= rxd0_length_fifo_q;

	test_rxd0_state_out 		<= rxd0_state_out;
	
	test_TSF_DS_PortNum 	<= TSF_DS_PortNum;
	test_TSF_OutputP_ready 	<= TSF_OutputP_ready;
	test_TSF_Bcast 			<= TSF_Bcast;
	--outputs to table from SF_table_interface
	test_SFT_req_out 		<= SFT_req_out;
	test_SFT_RDone 			<= SFT_RDone;
	test_SFT_SportN 		<= SFT_SportN;
	test_SFT_DMac_add_out 	<= SFT_DMac_add_out;
	test_SFT_SMac_add_out 	<= SFT_SMac_add_out;

	clk50_RX <= clk50;
	clk50_SF <= clk50;
	clk50_SM <= clk50;
	clk50_TX <= clk50;
	
--	reset <= '0';
	process(reset_key)
		begin 
			if (reset_key = '0') then
				reset_next <= '1';
			else
				reset_next <= '0';
			end if;
--		if (clk50'event and clk50='1') then
--		end if;
	end process;
	
	process(clk50, reset_next)
		begin 
		if (clk50'event and clk50='1') then
--			reset <= reset_next;
			reset_RX <= reset_next;
			reset_SF <= reset_next;
			reset_SM <= reset_next;
			reset_TX <= reset_next;
			reset_out <= reset_next;
		end if;
	end process;
	
end TX_RCV;